A speckle-based CMOS sensor for arbitrary surface movement detection with correlated double sampling and gain error correction

We present a CMOS sensor for accurate tracking of speckle movements on arbitrary surfaces. The sensor is made of a pair of comb filters with a pitch of 5.6 mu m and decayed by 90 degrees to produce quadrature signals. The readout circuit is a 60 dB amplification chain with offset and KTC noise compensation. Integrated into a 180nm CMOS process, the sensor and readout circuit occupy an area of about 0.1 mm(2) and consume 24 mu W at full speed of 64 ksample/s. The direction and frequency of the quadrature signals are resolved externally by zero- crossing detection, giving an accuracy of about 5 mu m. Thanks to a careful layout for gain error minimization, and the use of KTC noise cancellation, a negligible residual drift was observed, and a minimal displacement of 5 mu m was measured

Feature article: High sensitivity acquisition of GNSS signals with secondary code on FPGAs

The modern global navigation satellite systems (GNSS) signals, such as the Global Positioning System (GPS) L5 and L1C, and Galileo E5 and E1, have brought several innovations: the introduction of a pilot channel that does not contain any data to allow very long coherent integrations; the introduction of a secondary code to offer better cross-correlations, to facilitate the synchronization with the data, and to help interference mitigation; the introduction of new modulations to reduce the impact of multipath; and the use of higher chipping rates to have better accuracy and interference mitigatio

A Background Calibration Method for DAC Mismatch Correction in Multibit Sigma-Delta Modulators

A topology for the calibration of DAC errors in multi-bit sigma delta modulators is presented. The proposed technique enables the calibration to proceed in the background. In this technique, two DACs are used in a time-interleaved fashion. One DAC is calibrated at a time while the other is connected to the modulator. The technique is demonstrated by a design in UMC 0.18 µm CMOS technology which shows a very competitive figure of merit of 78fJ/Conv-Step. The extensive simulation results are presented to validate the results

A DAC Mismatch Calibration Technique for Multibit Sigma Delta Modulators

A technique for the calibration of DAC (digital to analog converter) mismatch errors in multi-bit Sigma Delta modulators (SDM) is presented. It consists of two parts: the first is a measurement technique to obtain the relative mismatch of each feedback DAC element. The second is a correction method applied to the modulator output to correct for the effect of DAC non linearity. The proposed technique works completely in the background. The paper presents a detailed analysis of the possible error sources affecting the accuracy of the calibration, as well as a comparison with other state of the art techniques. The technique is applied to a 3rd order SDM showing almost ideal characteristics after calibration

Design and Optimization of a Low Power and Fast Response Viscometer Used for Determination of the Natural Gas Wobbe Index

This paper reports on the design of a microsystem-based thermal gas viscometer used for the determination of the quality of natural gas and its optimization through modification of its two main components: the hotplate and the capillary tube. Features, such as ultra-low power consumption (95%), robustness, and cost-effective mass production are the key outcome from this optimization. Two different technologies were investigated for the integrated hotplate: thick film technology using screen printing on a ceramic substrate and silicon technology based on thin films’ deposition and silicon micromachining. The sensors have been evaluated both numerically and experimentally for gas mixtures composed of nitrogen, methane, and ethane. The sensor with silicon hotplate exhibited superior performances in terms of power consumption, thermal time constant, and reproducibility of manufacturing process. The impact of the geometry of the hotplate on the performance of the sensor was investigated and the optimum design identified. The electro-thermo-mechanical tests confirmed its long-term stability. Finally, the reduction of the response time of the sensor was evaluated by modifying the diameter of its capillary tube. The experimental results showed that by increasing the diameter of capillary tube from 20 to $30~\mu \text{m}$ , the response time of the sensor decreased from 60 to 25 s

La Lanterne : journal politique quotidien

05 janvier 19021902/01/05 (N9023,A25)

Dual Channel Optimization of Tracking Schemes for E1 CBOC Signal

New generation of satellite navigation signals, such as AltBOC (Alternative Binary Offset Keying), CBOC (Composite Binary Offset Keying) and TMBOC (Time Multiplex Binary Offset Keying) bring enhancements in the tracking process, such as more signal power, better multipath mitigation capabilities and more robust navigation. Moreover, one of the most important improvement they bring into the GNSS story is the presence of the two channels: data and pilot. The pilot channel, although dataless, carries the same information about the frequency, carrier and code phase as the data channel.Therefore, the information from both channels can be used to improve the tracking performance. In this context, the main point that is addressed in this paper is the optimization of the data/pilot combining tracking strategies in order to increase tracking stability, accuracy and robustness. Towards this end, non-coherent and coherent data/pilot combining strategies with different weights on each channel are presented, and the outputs from the DLL and PLL tracking loops using different discriminator types are analyzed and discussed. Moreover, an investigation for an optimal trade-off between the minimal tracking error and the best stability is reported with the corresponding results discussed. © 2011 IEEE

An efficient initialization mechanism of neurons for Winner Takes All Neural Network implemented in the CMOS technology

The paper presents a new initialization mechanism based on a Convex Combination Method (CCM) for Kohonen self-organizing Neural Networks (NNs) realized in the CMOS technology. A proper selection of initial values of the neuron weights exhibits a strong impact on the quality of the overall learning process. Unfortunately, in case of real input data, e.g. biomedical data, proper initialization is not easy to perform, as an exact data distribution is usually unknown. Bad initialization causes that even 70%-80% of neurons remain inactive, which increases the quantization error and thus limits the classification abilities of the NN. The proposed initialization algorithm has a couple of important advantages. Firstly, it does not require a knowledge of data distribution in the input data space. Secondly, there is no necessity for an initial polarization of the neuron weights before starting the learning process. This feature is very convenient in case of transistor level realizations. In this case the programming lines, which in other approaches occupy a large chip area, are not required. We proposed a modification of the original CCM algorithm. A new parameter which in the proposed analog CMOS realization is represented by an external current, allows to fit the behavior of the mechanism to NNs containing different numbers of neurons. The investigations show that the modified CCM operates properly for the NN containing even 250 neurons. A single CCM block realized in the CMOS 180 nm technology occupies an area of 300 mu m(2) and dissipates an average power of 20 mu W and at data rate of up to 20 MHz. (C) 2015 Elsevier Inc. All rights reserved